The rapid development of semiconductor technology is characterized by permanently increasing clock rates given simultaneous enlargement of the chip area, of the number of gates, and of the dissipated power. In highly parallel bus systems, the task of transmitting signals very fast and with low dissipated power despite greater line lengths therefore occurs. In bus systems, the information on highly parallel bus lines are detected and evaluated in the form of voltage or current levels.
Levels are often transmitted with the full supply voltage swing in the voltage evaluation. A reduction of the dissipated power can be achieved by lowering the level; this, however, reduces the transmission speed. The voltage transmission given extremely long lines is becoming increasingly problematical with respect to the power consumption and the speed. Long lines with level changes on the order of magnitude of the supply voltage also cause very serious problems in view of line crosstalk. Although modified forms of voltage evaluation reduce the voltage swing and are characterized by a low dissipated power, they are very sensitive to capacitive inputs.
In evaluation of current, a current is transmitted and only a minimal voltage swing that approaches zero in the ideal case arises, as a result of which the line crosstalk is drastically reduced. Specifically given very long lines, this principle is also superior to the voltage evaluation with respect to the dissipated power and speed.
German Letters Patent DE 44 30 631 C1 discloses a circuit arrangement for power reduction in an integrated circuit wherein a bus line with a current evaluation circuit is provided.